Pantheon allows you to create and define customized PCB / Hybrid / RF design rules, including a flexible set of net, component, padstack, and technology rules. During design layout, Pantheon automatically verifies the printed circuit board database against the predefined design rules. Pantheon also includes a post-processing set of database design rule checks. You can fully verify routing, net topology, area fills, tear drops, testpoints, geometries, component placement, and physical layers. Pantheon checks geometries for required and incorrect attributes, verifies nets for clearance and constraint violations, and examines connections for floating area fill or antenna traces.

Violations are compiled in a tabulated report with a brief summary of each violation. Pantheon can display violations separately or simultaneously on-screen to assist in problem resolution. 

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